The present invention relates to semiconductor devices, and more particularly, to a technique effectively applied to a semiconductor device including a laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET).
In recent years, mobile communication devices (which are the so-called mobile phones) using a communication system, such as a global system for mobile communications (GSM) system, a personal communications service (PCS) system, a personal digital cellular (PDC) system, or a code separation multiple access (CDMA) system, have been widespread.
In general, this kind of mobile communication device includes an antenna for radiating and receiving radio waves, a high-frequency power amplifier (radio frequency (RF) power module) for amplifying a power-modulated high-frequency signal to supply the amplified signal to the antenna, a receiver for processing the high-frequency signal received by the antenna, a controller for controlling these components, and a cell (battery) for applying a power-supply voltage to these components.
The above high-frequency power amplifier is required to have a high breakdown resistance against large variations in load. An amplification device, such as a high-frequency power amplifier, uses a number of laterally diffused MOS (LDMOS) transistors.
For example, the following Patent Document 1 (Japanese Unexamined Patent Publication No. 2010-50219) discloses a semiconductor device which includes a gate oxide film (24a) and a gate electrode (25a) formed over an N-type epitaxial layer (12) of a LDMOS portion (10a). In an interlayer insulating layer (14) of the LDMOS portion (10a), contact wirings (26a to 26c) are formed to electrically coupling each source electrode or each drain electrode to P+-type regions (17a to 17c) or an N+-type region (18).
The following Patent Document 2 (Japanese Unexamined Patent Publication No. 2009-32968) discloses a semiconductor device using a drain region (5) of a LDMOS as a cathode region (11) of a diode, and a back gate region (4) of the LDMOS as an anode region (14) of the diode. In the semiconductor device, a drain electrode (9) electrically coupled to the drain region (5) and a source electrode (8) electrically coupled to the back gate region (4) are formed in contact holes of an interlayer insulating layer (10).
The following Patent Document 3 (Japanese Unexamined Patent Publication No. 2007-173314) discloses a semiconductor device which includes a p-type punched layer (4) for electrically coupling a source region of a LDMOSFET to a source backside electrode (36) formed at the backside of a substrate (1). The p-type punched layer (4) is formed of a p-type polycrystal silicon film having a low resistance and doped with impurities in a high concentration, or a metal film having a low resistance. A source wiring for electrically coupling sources of basic cells of the above LDMOSFETs is only a wiring 24A. The number of wiring layers forming a source wiring is set smaller than that of wiring layers forming drain wirings (interconnects 24B, 29B, and 33).
In the description of the present application, reference numerals in parentheses indicate respective elements disclosed in each patent document.